View BR93A86-WM_4577732.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Serial EEPROM Series
High Reliability Series EEPROMs Microwire BUS
BR93L-W Series, 93A-WM Series, BR93H-WC Series
No.09001EET03
ROHM's series of serial EEPROMs represent the highest level of reliability on the market. A double cell structure provides a failsafe method of data reliability, while a double reset function prevents data miswriting. In addition, gold pads and gold wires are used for internal connections, pushing the boundaries of reliability to the limit. BR93L-W Series are assort 1Kbit16Kbit. BR93A-WM Series are possible to operate at 105 and are assorted with 1K16Kbit. BR93H-WC Series are possible to operate at 125, are assorted with 2K16Kbit.
Contents BR93L-W Series
BR93L46-W, BR93L56-W, BR93L66-W, BR93L76-W, BR93L86-W
BR93A-WM Series
BR93A46-WM, BR93A56-WM, BR93A66-WM, BR93A76-WM, BR93A86-WM
P2
BR93H-WC Series
BR93H56-WC, BR93H66-WC, BR93H76-WC, BR93H86-WC
P22
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
1/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series Serial EEPROM Series
Technical Note
High Reliability Series EEPROMs Microwire BUS
BR93L-W Series, 93A-WM Series
Description BR93L-W Series, BR93A-WM Series are serial EEPROM of serial 3-line interface method Features 1) 3-line communications of chip select, serial clock, serial data input / output (the case where input and output are shared) 2) Actions available at high speed 2MHz clock2.5~5.5V 3) Speed write available (write time 5ms max. 4) Same package and pin layout from 1Kbit to 16Kbit 5) 1.8~5.5V (BR93L-W Series), 2.55.5V(BR93A-WM Series) single power source action 6) Highly reliable connection by Au pad and Au wire 7) Address auto increment function at read action 8) Write mistake prevention function Write prohibition at power on Write prohibition by command code Write mistake prevention function at low voltage 9) Program cycle auto delete and auto end function 10) Program condition display by READY / BUSY 11) Low current consumption At write action (at 5V) : 1.2mA (Typ.) At read action (at 5V) : 0.3mA (Typ.) At standby action (at 5V) : 0.1A (Typ.)(CMOS input) 12) TTL compatible( input / output s) *1 13) Compact package SOP8/SOP-J8/SSOP-B8/TSSOP-B8/MSOP8/TSSOP-B8J 14) Data retention for 40 years 15) Data rewrite up to 1,000,000 times 16) Data at shipment all addresses FFFFh
*1 Only SOP8, SOP-J8, MSOP8 for BR93A-WM
BR93L, BR93A Series
Capacity Bit format Type Power source voltage 1.85.5V 1.85.5V 1.85.5V 1.85.5V 1.85.5V 2.55.5V 2.55.5V 2.55.5V 2.55.5V 2.55.5V SOP8 F RF SOP-J8 FJ RFJ SSOP-B8 FV RFV TSSOP-B8 FVT RFVT MSOP8 RFVM TSSOP-B8J RFVJ
Package type 1Kbit 2Kbit 4Kbit 8Kbit 16Kbit 1Kbit 2Kbit 4Kbit 8Kbit 16Kbit 64x16 128x16 256x16 512x16 1Kx16 64x16 128x16 256x16 512x16 1Kx16 BR93L46-W BR93L56-W BR93L66-W BR93L76-W BR93L86-W BR93A46-WM BR93A56-WM BR93A66-WM BR93A76-WM BR93A86-WM
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
2/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
Absolute Maximum Ratings(Ta=25,BR93L-W) Parameter Symbol Impressed voltage VCC
Technical Note
Limits -0.3+6.5 450 (SOP8) *1 450 (SOP-J8) *2 300 (SSOP-B8) *3 330 (TSSOP-B8) *4 310 (MSOP8) *5 310 (TSSOP-B8J) *6
Unit V
Permissible dissipation
Pd
mW
Storage temperature range Action temperature range Terminal voltage
Tstg Topr
-65+125 -40+85 -0.3VCC+0.3
V
* When using at Ta=25 or higher, 4.5mW(*1,*2), 3.0mW(*3) 3.3mW(*4), 3.1mW(*5, 6), to be reduced per 1.
Absolute Maximum Ratings (Ta=25,BR93A-WM) Parameter Symbol Impressed voltage Permissible dissipation Storage temperature range Action temperature range Terminal voltage VCC Pd Tstg Topr
Limits -0.3+6.5 450 (SOP8)
*1
Unit V mW V
450 (SOP-J8) *2 310 (MSOP8) *3 -65+125 -40+105 -0.3VCC+0.3
* When using at Ta=25 or higher, 4.5mW(*1,*2), 3.1 mW(*3) to be reduced per 1.
Memory cell characteristics (VCC=1.85.5V,BR93L-W) Parameter Number of data rewrite times *1 Data hold years *1
Shipment data all address FFFFh *1 Not 100% TESTED
Limit Min. 1,000,000 40 Typ. Max. -
Unit Times Years
Condition Ta=25 Ta=25
Memory cell characteristics (VCC=2.55.5V,BR93A-WM) Parameter Number of data rewrite times *1 Data hold years *1
Shipment data all address FFFFh *1 Not 100% TESTED
Limit Min. 1,000,000 100,000 40 10 Typ. Max.
Unit Times Years
Condition Ta25 Ta105 Ta25 Ta50
Recommended action conditions (BR93L-W) Parameter Power source voltage Input voltage
Symbol VCC VIN
Limits 1.85.5 0VCC
Unit
V
Recommended action conditions (BR93A-WM) Parameter Symbol Power source voltage Input voltage VCC VIN
Limits 2.55.5 0VCC
Unit V
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
3/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
Technical Note
Electrical characteristics (Unless otherwise specified, VCC=2.55.5V, Ta=-40+85, BR93L-W, Ta=-40+105, BR93A-WM) Limits Parameter Symbol Unit Condition Min. Typ. Max. "L" input voltage 1 "L" input voltage 2 "H" input voltage 1 "H" input voltage 2 "L" output voltage 1 "L" output voltage 2 "H" output voltage 1 "H" output voltage 2 Input leak current Output leak current Current consumption at action Standby current VIL1 VIL2 VIH1 VIH2 VOL1 VOL2 VOH1 VOH2 ILI ILO ICC1 ICC2 ICC3 ISB -0.3 -0.3 2.0 0.7 x VCC 0 0 2.4 VCC-0.2 -1 -1 +0.8 0.2 x VCC VCC+0.3 VCC+0.3 0.4 0.2 VCC VCC +1 +1 3.0 1.5 4.5 2 V V V V V V V V A A mA mA mA A 4.0VVCC5.5V VCC4.0V 4.0VVCC5.5V VCC4.0V IOL=2.1mA, 4.0VVCC5.5V IOL=100A IOH=-0.4mA, 4.0VVCC5.5V IOH=-100A VIN=0VVCC VOUT=0VVCC, CS=0V fSK=2MHz, tE/W=5ms (WRITE) fSK=2MHz (READ) fSK=2MHz, tE/W=5ms (WRAL, ERAL) CS=0V, DO=OPEN
Radiation resistance design is not made.
(Unless otherwise specified, VCC=1.82.5V, Ta=-40+85, BR93L-W) Limits Parameter Symbol Unit Min. Typ. Max. "L" input voltage "H" input voltage "L" output voltage "H" output voltage Input leak current Output leak current Current consumption at action Standby current VIL VIH VOL VOH ILI ILO ICC1 ICC2 ICC3 ISB -0.3 0.7 x VCC 0 VCC-0.2 -1 -1 0.2 x VCC VCC+0.3 0.2 VCC +1 +1 1.5 0.5 2 2 V V V V A A mA mA mA A IOL=100A IOH=-100A VIN=0VVCC
Condition
VOUT=0VVCC, CS=0V fSK=500kHz, tE/W=5ms (WRITE) fSK=500kHz (READ) fSK=500kHz, tE/W=5ms (WRAL, ERAL) CS=0V, DO=OPEN
Radiation resistance design is not made.
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
4/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
Technical Note
Action timing characteristics (BR93L-W, Ta=-40+85, VCC=2.55.5V, BR93A-WM, Ta=-40+105, VCC=2.55.5V) 2.5VVCC5.5V Parameter Symbol Unit Min. Typ. Max. SK frequency fSK 2 MHz SK "H" time tSKH 230 ns SK "L" time tSKL 230 ns CS "L" time tCS 200 ns CS setup time tCSS 50 ns DI setup time tDIS 100 ns CS hold time tCSH 0 ns DI hold time tDIH 100 ns Data "1" output delay time tPD1 200 ns Data "0" output delay time tPD0 200 ns Time from CS to output establishment tSV 150 ns Time from CS to High-Z tDF 150 ns Write cycle time tE/W 5 ms (BR93L-W, Ta=-40+85, VCC=1.82.5V) Parameter SK frequency SK "H" time SK "L" time CS "L" time CS setup time DI setup time CS hold time DI hold time Data "1" output delay time Data "0" output delay time Time from CS to output establishment Time from CS to High-Z Write cycle time Symbol fSK tSKH tSKL tCS tCSS tDIS tCSH tDIH tPD1 tPD0 tSV tDF tE/W Min. 0.8 0.8 1 200 100 0 100 1.8VVCC2.5V Typ. Max. 500 0.7 0.7 0.7 200 5 Unit kHz us us us ns ns ns ns us us us ns ms
Sync data input / output timing
CS
tCSS tSKH tSKL tCSH
SK
tDIS tDI H
DI
t PD0 tPD1
DO(READ)
tDF
DO(WRITE)
STATUS VALID
Fig.1 Sync data input / output timing Data is taken by DI sync with the rise of SK. At read action, data is output from DO in sync with the rise of SK. The status signal at write (READY / BUSY) is output after tCS from the fall of CS after write command input, at the area DO where CS is "H", and valid until the next command start bit is input. And, while CS is "L", DO becomes High-Z. After completion of each mode execution, set CS "L" once for internal circuit reset, and execute the following action mode.
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
5/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
BR93L-W Characteristic data (The following characteristic data are Typ. values.)
Technical Note
Fig.2 H output voltage VIH(CS,SK,DI)
Fig.3 H input voltage VIL(CS,SK,DI)
Fig.4
L output voltage VOL-IOL(Vcc=1.8V)
Fig.5 L output voltage VOL-IOL(Vcc=2.5V)
Fig.6 L output voltage VOL-IOL(Vcc=4.0V)
Fig.7 H output voltage VOH-IOH(Vcc=1.8V)
Fig.8 H output voltage VOH-IOH(Vcc=2.5V)
Fig.9 H output voltage VOH-IOH(Vcc=4.0V)
Fig.10
Input leak current ILI(CS,SK,DI)
Fig.11 Output leak current ILO (DO)
Fig.12
Current consumption at WRITE action ICC1 (WRITE, fSK=2MHz)
Fig.13 Consumption current at READ action
ICC2 (READ, fSK=2MHz)
Fig.14
Consumption current at WRAL action ICC3 (WRAL, fSK=2MHz)
Fig.15 Current consumption at WRITE action
ICC1 (WRITE, fSK=500kHz)
Fig.16 Consumption current at READ action
ICC2 (READ, fSK=500kHz)
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
6/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
BR93L-W Characteristic data (The following characteristic data are Typ. values.)
Technical Note
Fig.17
Consumption current at WRAL action ICC3 (WRAL, fSK=500kHz)
Fig.18
Consumption current at standby action ISB
Fig.19 SK frequency fSK
Fig.20
SK high time tSKH
Fig.21
SK low time tSKL
Fig.22
CS low time tCS
Fig.23
CS hold time tCSH
Fig.24
CS setup time tCSS
Fig.25
DI hold time tDIH
Fig.26
DI setup time tDIS
Fig.27
Data "0" output delay time tPD0
Fig.28
Output data "1" delay time tPD1
Fig.29 Time from CS to output establishment tSV
Fig.30 Time from CS to High-Z tDF
Fig.31 Write cycle time tE/W
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
7/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
BR93A-WM Characteristic data (The following characteristic data are Typ. values.)
Technical Note
Fig.32 H output voltage VIH(CS,SK,DI)
Fig.33 H input voltage VIL(CS,SK,DI)
Fig.34
L output voltage VOL-IOL(Vcc=2.5V)
Fig.35 L output voltage VOL-IOL(Vcc=4.0V)
Fig.36
H output voltage VOH-IOH(Vcc=2.5V)
Fig.37 H output voltage VOH-IOH(Vcc=4.0V)
Fig.38 Input leak current ILI(CS,SK,DI)
Fig.39 Output leak current ILO(DO)
Fig.40
Current consumption at WRITE action Icc1(WRITE, fSK=2MHz)
Fig.41 Consumption current at READ action
Icc2(READ, fSK=2MHz)
Fig.42
Consumption current at WRAL action Icc3(WRAL, fSK=2MHz)
Fig.43
Consumption current at standby action ISB
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
8/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
BR93A-WM Characteristic data (The following characteristic data are Typ. values.)
Technical Note
Fig.44 SK frequency fSK
Fig.45
SK high time tSKH
Fig.46 SK low time tSKL
Fig.47
CS low time tCS
Fig.48 CS hold time tCSH
Fig.49 CS setup time tCSS
Fig.50 DI hold time tDIH
Fig.51 DI setup time tDIS
Fig.52 Data "0" output delay time tPD0
Fig.53
Output data "1" delay time tPD1
Fig.54 Time from CS to output establishment tSV
Fig.55 Time from CS to High-Z tDF
Fig.56 Write cycle time tE/W
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
9/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
Block diagram
Technical Note
CS
Command decode Control
Power source voltage detection
SK
Clock generation
Write prohibition Address buffer
6bit 7bit 8bit 9bit 10bit
High voltage occurrence
DI
Command register
Address decoder
6bit 7bit 8bit 9bit 10bit
Data register DO Dummy bit
16bit
R/W amplifier
16bit
1,024 bit 2,048 bit 4,096 bit 8,192 bit 16,384 bit EEPROM
Fig.57 Block diagram
Pin assignment and function
NC GND DO DI Vcc NC NC GND
BR93LXXRF-W/AXXRF-WM:SOP8
BR93LXXF-W/AXXF-WM:SOP8 BR93LXXFJ-W/AXXFJ-WM:SOP-J8 BR93LXXFV-W:SSOP-B8* BR93LXXFVT-W:TSSOP-B8*
BR93LXXRFJ-W/AXXRFJ-WM:SOP-J8 BR93LXXRFV-W:SSOP-B8 BR93LXXRFVT-W:TSSOP-B8 BR93LXXRFVM-W/AXXRFVM-WM:MSOP8 BR93LXXRFVJ-W:TSSOP-B8J
NC
Vcc
CS
SK
CS
SK
DI
DO
*BR93L46/56/66-W
Fig.58 Pin assignment diagram Pin name VCC GND CS SK DI DO NC I/O Input Input Input Output Function Power source All input / output reference voltage, 0V Chip select input Serial clock input Start bit, ope code, address, and serial data input Serial data output, READY / BUSY internal condition display output Non connected terminal, Vcc, GND or OPEN
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
10/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
Technical Note
Description of operations Communications of the Microwire Bus are carried out by SK (serial clock), DI (serial data input),DO (serial data output) ,and CS (chip select) for device selection. When to connect one EEPROM to a microcontroller, connect it as shown in Fig.59(a) or Fig.59(b). When to use the input and output common I/O port of the microcontroller, connect DI and DO via a resistor as shown in Fig.59(b) (Refer to pages 17/35.), and connection by 3 lines is available. In the case of plural connections, refer to Fig. 59 (c).
Microcontroller Microcontroller CS SK DO DI BR93LXX /AXX CS SK DI DO Microcontroller CS SK DO BR93LXX /AXX CS SK DI
CS SK DI DO CS3 CS1 CS0 SK DO DI
DO
CS SK DI DO
Device 1
Device 2
Fig.59-(a) Connection by 4 lines
Fig.59-(b) Connection by 3 lines
Fig.59-(c) Connection example of plural devices
Fig.59 Connection method with microcontroller Communications of the Microwire Bus are started by the first "1" input after the rise of CS. This input is called a start bit. After input of the start bit, input ope code, address and data. Address and data are input all in MSB first manners. "0" input after the rise of CS to the start bit input is all ignored. Therefore, when there is limitation in the bit width of PIO of the microcontroller, input "0" before the start bit input, to control the bit width.
Command mode
Command Read (READ) Write enable (WEN) Write (WRITE) Write all (WRAL) Write disable (WDS) Erase (ERASE)
*2 *2 *1
Start bit 1 1 1 1 1 1
Ope code 10 00 01 00 00 11
BR93L46-W BR93A46-WM
A5,A4,A3,A2,A1,A0 1 1 ****
Address BR93L56/66-W BR93A56/66-WM
A7,A6,A5,A4,A3,A2,A1,A0 1 1 ******
BR93L76/86-W BR93A76/86-WM
A9,A8,A7,A6,A5,A4,A3,A2,A1,A0 1 1 ********
D15~D0(READ DATA)
A5,A4,A3,A2,A1,A0 0 0 1 0 **** ****
A7,A6,A5,A4,A3,A2,A1,A0 0 0 1 0 ****** ******
A9,A8,A7,A6,A5,A4,A3,A2,A1,A0 0 0 1 0 ******** ********
D15~D0(WRITE DATA) D15~D0(WRITE DATA)
A5,A4,A3,A2,A1,A0
A7,A6,A5,A4,A3,A2,A1,A0
A9,A8,A7,A6,A5,A4,A3,A2,A1,A0
Chip erase (ERAL) 1 00 1 0 **** 1 0 ****** 1 0 ******** Input the address and the data in MSB first manners. A7 of BR93L56-W/A56-WM becomes Don't Care. As for *, input either VIH or VIL. A9 of BR93L76-W/A76-WM becomes Don't Care. *Start bit Acceptance of all the commands of this IC starts at recognition of the start bit. The start bit means the first "1" input after the rise of CS. *1 As for read, by continuous SK clock input after setting the read command, data output of the set address starts, and address data in significant order are sequentially output continuously. (Auto increment function) *2 When the read and the write all commands are executed, data written in the selected memory cell is automatically deleted, and input data is written.
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
11/40
2009.12 - Rev.E
CS SK DI DO Device 3 Data
BR93L-W Series, 93A-WM Series, BR93H-WC Series
Timing chart 1) Read cycle (READ)

Technical Note
CS
*1
SK
1
2
4
n
n+1
DI
1
1
0
Am

A1
A0
*2

BR93L46-W/A46-WM : n=25, m=5 BR93L56-W/A56-WM : n=27, m=7 BR93L66-W/A66-WM BR93L76-W/A76-WM : n=29, m=9 BR93L86-W/A86-WM
DO High-Z
0
D15
D14
D1
D0
D15 D14
*1 Start bit When data "1" is input for the first time after the rise of CS, this is recognized as a start bit. And when "1" is input after plural "0" are input, it is recognized as a start bit, and the following operation is started. This is common to all the commands to described hereafter.
Fig. 60 Read cycle
When the read command is recognized, input address data (16bit) is output to serial. And at that moment, at taking A0, in sync with the rise of SK, "0" (dummy bit) is output. And, the following data is output in sync with the rise of SK. This IC has an address auto increment function valid only at read command. This is the function where after the above read execution, by continuously inputting SK clock, the above address data is read sequentially. And, during the auto increment, keep CS at "H".
2) Write cycle (WRITE)

tCS
CS

STATUS
SK
1
2
4

n
DI
1
0
1
Am
A1
A0
D15
D14
D1
D0
tSV
BR93L46-W/A46-WM : n=25, m=5 BR93L56-W/A56-WM : n=27, m=7 BR93L66-W/A66-WM BR93L76-W/A76-WM : n=29, m=9 BR93L86-W/A86-WM
DO High-Z
BUSY READY
tE/W
Fig.61 Write cycle
In this command, input 16bit data (D15~D0) are written to designated addresses (Am~A0). The actual write starts by the fall of CS of D0 taken SK clock. When STATUS is not detected, (CS="L" fixed) Max. 5ms in conformity with tE/W, and when STATUS is detected (CS="H"), all commands are not accepted for areas where "L" (BUSY) is output from D0, therefore, do not input any command.
3) Write all cycyle (WRAL)

tCS
CS

STATUS
SK
1
2
5

n
DI
1
0
0
0
1

D15
D14

D1
D0
tSV BUSY READY
BR93L46-W/A46-WM : n=25 BR93L56-W/A56-WM : n=27 BR93L66-W/A66-WM BR93L76-W/A76-WM : n=29 BR93L86-W/A86-WM
DO High-Z
Fig.62 Write all cycle
tE/W
In this command, input 16bit data is written simultaneously to all adresses. Data is not written continuously per one word but is written in bulk, the write time is only Max. 5ms in conformity with tE/W.
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
12/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
4) Write enable (WEN) / disable (WDS) cycle
Technical Note
CS
SK
1
2
3
4
5
6
7
8
n
ENABLE=1 1 DISABLE=0 0 DI 1 0 0

BR93L46-/A46-WM : n=9 BR93L56-W/A56-WM : n=11 BR93L66-W/A66-WM BR93L76-W/A76-WM : n=13 BR93L86-W/A86-WM
DO High-Z
Fig.63 Write enable (WEN) / disable (WDS) cycle At power on, this IC is in write disable status by the internal RESET circuit. Before executing the write command, it is necessary to execute the write enable command. And, once this command is executed, it is valid unitl the write disable command is executed or the power is turned off. However, the read command is valid irrespective of write enable / diable command. Input to SK after 6 clocks of this command is available by either "H" or "L", but be sure to input it. When the write enable command is executed after power on, write enable status gets in. When the write disable command is executed then, the IC gets in write disable status as same as at power on, and then the write command is canceled thereafter in software manner. However, the read command is executable. In write enable status, even when the write command is input by mistake, write is started. To prevent such a mistake, it is recommended to execute the write disable command after completion of write.
5) Erase cycle timing (ERASE)

tCS
CS
STATUS

SK
1
2
4
n

DI
1
1
1
Am

A3
A2
A1
A0
tSV BUSY READY tE/W

BR93L46-W/A46-WM : n=9, m=5 BR93L56-W/A56-WM : n=11, m=7 BR93L66-W/A66-WM BR93L76-W/A76-WM : n=13, m=9 BR93L86-W/A86-WM
DO
High-Z
Fig.64 Erase cycle timing In this command, data of the designated address is made into "1". The data of the designated address becomes "FFFFh". Actual ERASE starts at the fall of CS after the fall of A0 taken SK clock. In ERASE, status can be detected in the same manner as in WRITE command.
6) Chip erase cycle timing (ERAL)

tCS
CS
STATUS

SK
1
2
4
n
DI
1
0
0
1
0
tSV

BR93L46-W/A46-WM : n=9 BR93L56-W/A56-WM : n=11 BR93L66-W/A66-WM BR93L76-W/A76-WM : n=13 BR93L86-W/A86-WM
DO
High-Z
BUSY READY tE/W
Fig.65 Chip erase cycle timing In this command, data of all addresses is erased. Data of all addresses becomes "FFFFh". Actual ERASE starts at the fall of CS after the falll of the n-th clock from the start bit input. In ERAL, status can be detected in the same manner as in WRITE command.
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
13/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
Application 1) Method to cancel each command READ
Start bit
1bit
Technical Note
Ope code
2bit
Address
6bit
*1
Data
16bit
(In the case of BR93L46-W/A46-WM)
1 Address is 8 bits in BR93L56-W/A56-WM, BR93L-66W/A66-WM Address is 10 bits in BR93L76-W/A76-WM, BR93L86-W/A86-WM
Cancel is available in all areas in read mode. Method to cancelcancel by CS="L"
Fig.66 READ cancel available timing
WRITE, WRAL
25 Rise of clock SK DI 24 D1 25 D0
*2
Enlarged figure
*1
Start bit
1bit
Ope code
2bit
Address
6bit
Data
16bit
tE/W
b
(In the case of BR93L46-W/A46-WM)
a
aFrom start bit to 25 clock rise2 Cancel by CS="L" b25 clock rise and after2 Cancellation is not available by any means. If Vcc is made OFF in this area, designated address data is not guaranteed, therefore write once again. And when SK clock is input continuously, cancellation is not available. *1
Address is 8 bits in BR93L56-W/A56-WM, BR93L66-W/A66-WM Address is 10 bits in BR93L76-W/A76-WM BR93L86-W/A86-WM *2 27 clocks in BR93L56-W/A56-WM, BR93L66-W/A66-WM 29 clocks in BR93L76-W/A76-WM BR93L86-W/A86-WM
29 Rise of clock
SK DI D1 28 29 D0
*2 30 31
b c a Enlarged figure
Start bit
1bit
Ope code
2bit a
Address *1
10bit
Data
16bit b
tE/W
c
(In the case of BR93L86-W/A86-WM)
aFrom start bit to 29 clock rise Cancel by CS="L" b29 clock rise and after Cancellation is not available by any means. If Vcc is made OFF in this area, designated address data is not guaranteed, therefore write once again. c30 clock rise and after Cancel by CS="L" However, when write is started in b area (CS is ended), cancellation is not available by any means. And when SK clock is output continuously is not available. Note 1) If Vcc is made OFF in this area, designated address data is not guaranteed, therefore write once again. Note 2) If CS is started at the same timing as that of the SK rise, write execution/cancel becomes unstable, therefore, it is recommended to fail in SK="L" area. As for SK rise, recommend timing of tCSS/tCSH or higher.
Fig.67 WRITE, WRAL cancel available timing
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
14/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
Technical Note
ERASE, ERAL
9 Rise of clock2
SK DI A1 8 9 A0
Enlarged figure
Start bit
1bit
Ope code
2bit
Address
6bit
*1
1/2 tE/W
(In the case of BR93L46-W/A46-WM)
a
b
1 Address is 8 bits in BR93L56-W/A56-WM, BR93L66-W/A66-WM Address is 10 bits in BR93L76-W/A76-WM 2 11 clocks in BR93L56-W/A56-WM, BR93L66-W/A66-WM 13 clocks in BR93L76-W/A76-WM
aFrom start bit to 9 clock rise2 Cancel by CS="L" b9 clock rise and after2 Cancellation is not available by any means. If Vcc is made OFF in this area, designated address data is not guaranteed, therefore write once again. And when SK clock is input continuously, cancellation is not available.
13 Rise of clock
SK DI D1 12 13
*2 14 15
a
b c Enlarged figure
Start bit
1bit
Ope code
2bit a
Address
10bit
*1
tE/W
(In the case of BR93L86-W/A86-WM)
b c
aFrom start bit to 13 clock rise Cancel by CS="L" b13 clock rise and after Cancellation is not available by any means. If Vcc is made OFF in this area, designated address data is not guaranteed, therefore write once again. c14 clock rise and after Cancel by CS="L" However, when write is started in b area (CS is ended), cancellation is not available by any means. And when SK clock is output continuously is not available.
Note 1) If Vcc is made OFF in this area, designated address data is not guaranteed, therefore write once again. Note 2) If CS is started at the same timing as that of the SK rise, write execution/cancel becomes unstable, therefore, it is recommended to fail in SK="L" area. As for SK rise, recommend timing of tCSS/tCSH or higher.
Fig.68 ERASE, ERAL cancel available timing
2) At standby Standby current When CS is "L", SK input is "L", DI input is "H", and even with middle electric potential, current does not increase. Timing As shown in Fig.69, when SK at standby is "H", if CS is started, DI status may be read at the rise edge. At standby and at power ON/OFF, when to start CS, set SK input or DI input to "L" status. (Refer to Fig.70)
CS=SK=DI="H" Wrong recognition as a start bit If CS is started when SK="L" or DI="L", a start bit is recognized correctly.
CS
Start bit input
CS
Start bit input
SK
SK
DI
DI
Fig.69 Wrong action timing
Fig.70 Normal action timing
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
15/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
3) Equivalent circuit
Output circuit
Input citcuit
RESET int. CS
Technical Note
CSint.
DO
OEint.
Fig.71 Output circuit (DO)
Input circuit
CS int. DI
Fig.72 Input circuit (CS)
Input circuit
CS int.
SK
Fig.73 Input circuit (DI)
Fig.74 Input circuit (SK)
4) I/O peripheral circuit 4-1) Pull down CS. By making CS="L" at power ON/OFF, mistake in operation and mistake write are prevented. Pull down resistance Rpd of CS pin To prevent mistake in operation and mistake write at power ON/OFF, CS pull down resistance is necessary. Select an appropriate value to this resistance value from microcontroller VOH, IOH, and VIL characteristics of this IC.
VOHM IOHM VIHE
Rpd
Microcontroller VOHM EEPROM VIHE

VOHM
Example) When VCC =5V, VIHE=2V, VOHM=2.4V, IOHM=2mA, from the equation , Rpd Rpd 2.4 2x10
-3
"H" output
IOHM
Rpd
"L" input
1.2 [k]
With the value of Rpd to satisfy the above equation, VOHM becomes 2.4V or higher, and VIHE (=2.0V), the equation is also satisfied.
Fig.75 CS pull down resistance
VIHE : EEPROM VIH specifications VOHM : Microcontroller VOH specifications IOHM : Microcontroller IOH specifications
4-2) DO is available in both pull up and pull down. Do output become "High-Z" in other READY / BUSY output timing than after data output at read command and write command. When malfunction occurs at "High-Z" input of the microcontroller port connected to DO, it is necessary to pull down and pull up DO. When there is no influence upon the microcontroller actions, DO may be OPEN. If DO is OPEN, and at timing to output status READY, at timing of CS="H", SK="H", DI="H", EEPROM recognizes this as a start bit, resets READY output, and DO="High-Z", therefore, READY signal cannot be detected. To avoid such output, pull up DO pin for improvement.
CS CS "H"
SK Enlarged DI D0
SK
DI
High-Z DO
BUSY
READY
DO BUSY
High-Z
CS=SK=DI="H" When DO=OPEN CS=SK=DI="H" When DO=pull up
Improvement by DO pull up DO
BUSY READY
Fig.76 READY output timing at DO=OPEN
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
16/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
Technical Note
Pull up resistance Rpu and pull down resistance Rpd of DO pin As for pull up and pull down resistance value, select an appropriate value to this resistance value from microcontroller VIH, VIL, and VOH, IOH, VOL, IOL characteristics of this IC.
Microcontroller VILM Rpu IOLE VOLE EEPROM
Rpu VOLE
VccVOLE IOLE VILM

"L" input "L" output
Example) When VCC =5V, VOLE=0.4V, IOLE=2.1mA, VILM=0.8V, from the equation , Rpu Rpu 50.4 2.1x10 2.2 [k]
-3
Fig.77 DO pull up resistance
With the value of Rpu to satisfy the above equation, VOLE becomes 0.4V or below, and with VILM(=0.8V), the equation is also satisfied. VOLE IOLE VILM : EEPROM VOL specifications : EEPROM IOL specifications : Microcontroller VIL specifications VOHE IOHE VIHM
Microcontroller VIHM IOHE
EEPROM
Rpd VOHE

VOHE Rpd "H" output
Example) When VCC =5V, VOHE=Vcc0.2V, IOHE=0.1mA, VIHM=Vccx0.7V from the equation , Rpd Rpd 50.2 0.1x10 48 [k]
-3
"H" input
Fig.78 DO pull down resistance
With the value of Rpd to satisfy the above equation, VOHE becomes 2.4V or below, and with VIHM (=3.5V), the equation is also satisfied. VOHE IOHE VIHM : EEPROM VOH specifications : EEPROM IOH specifications : Microcontroller VIH specifications
5) READY / BUSY status display (DO terminal) (common to BR93L46-W/A46-WM,BR93L56-W/A56-WM, BR93L66-W/A66-WM, BR93L76-W/A76-WM, BR93L86-W/A86-WM) This display outputs the internal status signal. When CS is started after tCS (Min.200ns) from CS fall after write command input, "H" or "L" is output.
R/B display"L" (BUSY) = write under execution After the timer circuit in the IC works and creates the period of tE/W, this time circuit completes automatically. And write to the memory cell is made in the period of tE/W, and during this period, other command is not accepted. R/B display = "H" (READY) = command wait status DO status Even after tE/W (max.5ms) from write of the memory cell, the following command is accepted. Therefore, CS="H" in the period of tE/W, and when input is in SK, DI, malfunction may occur, therefore, DI="L" in the area CS="H". (Especially, in the case of shared input port, attention is required.)
*Do not input any command while status signal is output. Command input in BUSY area is cancelled, but command input in READY area is accepted. Therefore, status READY output is cancelled, and malfunction and mistake write may be made.
DO status
CS
STATUS
SK
CLOCK WRITE INSTRUCTION High-Z
DI
tSV
READY BUSY
DO
Fig.79 R/B status output timing chart
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
17/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
Technical Note
6) When to directly connect DI and DO This IC has independent input terminal DI and output terminal DO, and separate signals are handled on timing chart, meanwhile, by inserting a resistance R between these DI and DO terminals, it is possible to carry out control by 1 control line.
Microcontroller DI/O PORT DI R DO EEPROM
Fig.80 DI, DO control line common connection Data collision of microcontroller DI/O output and DO output and feedback of DO output to DI input. Drive from the microcontroller DI/O output to DI input on I/O timing, and signal output from DO output occur at the same time in the following points. (1) 1 clock cycle to take in A0 address data at read command Dummy bit "0" is output to DO terminal. When address data A0 = "1" input, through current route occurs.
EEPROM CS input "H" EEPROM SK input A1 A0 Collision of DI input and DO output EEPROM DO output High-Z A1 A0 0 D15 D14 D13
EEPROM DI input
Microcontroller DI/O port
High-Z Microcontroller input
Microcontroller output
Fig.81 Collision timing at read data output at DI, DO direct connection (2) Timing of CS = "H" after write command. DO terminal in READY / BUSY function output. When the next start bit input is recognized, "HIGH-Z" gets in. Especially, at command input after write, when CS input is started with microcontroller DI/O output "L", READY output "H" is output from DO terminal, and through current route occurs. Feedback input at timing of these (1) and (2) does not cause disorder in basic operations, if resistance R is inserted.
EEPROM CS input
Write command

EEPROM SK input
Write command

EEPROM DI input
Write command READY
EEPROM DO output
Write command
BUSY
READY
High-Z
Collision of DI input and DO output
Microcontroller DI/O port
Write command Microcontroller output
BUSY
READY
Microcontroller input
Microcontroller output
Fig.82 Collision timing at DI, DO direct connection
Note) As for the case (2), attention must be paid to the following. When status READY is output, DO and DI are shared, DI="H" and the microcontroller DI/O="High-Z" or the microcontroller DI/O="H",if SK clock is input, DO output is input to DI and is recognized as a start bit, and malfunction may occur. As a method to avoid malfunction, at status READY output, set SK="L", or start CS within 4 clocks after "H" of READY signal is output.
CS
Start bit
SK
Because DI="H", set SK="L" at CS rise.
DI READY DO High-Z
Fig.83 Start bit input timing at DI, DO direct connection
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
18/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
Technical Note
Selection of resistance value R The resistance R becomes through current limit resistance at data collision. When through current flows, noises of power source line and instantaneous stop of power source may occur. When allowable through current is defined as I, the following relation should be satisfied. Determine allowable current amount in consideration of impedance and so forth of power source line in set. And insert resistance R, and set the value R to satisfy EEPROM input level VIH/VIL even under influence of voltage decline owing to leak current and so forth. Insertion of R will not cause any influence upon basic operations. (1) Address data A0 = "1" input, dummy bit "0" output timing (When microcontroller DI/O output is "H", EEPROM DO outputs "L", and "H" is input to DI) Make the through current to EEPROM 10mA or below. See to it that the level VIH of EEPROM should satisfy the following.
Conditions
Microcontroller EEPROM
VOHM VIHE VOHM IOHMxR + VOLE At this moment, if VOLE=0V, VOHM IOHMxR
DI/O PORT "H" output VOHM IOHM R
DI
DO VOLE "L" output
VIHE VOLE VOHM IOHM
R
VOHM IOHM
: EEPROM VIH specifications : EEPROM VOL specifications : Microcontroller VOH specifications : Microcontroller IOH specifications
Fig.84
Circuit at DI, DO direct connection (Microcontroller DI/O "H" output, EEPROM "L" output)
(2) DO status READY output timing (When the microcontroller DI/O is "L", EEPROM DO output "H", and "L" is input to DI) Set the EEPROM input level VIL so as to satisfy the following.
Conditions
Microcontroller "L" output DI/O PORT VOLM IOHM R DO VOHE "H" output DI EEPROM
VOLM VILE VOLM VOHE - IOLMxR As this moment, VOHE=Vcc VOLM Vcc - IOLMxR VILE VOHE VOLM IOLM Vcc - VOLM IOLM
: EEPROM VIL specifications : EEPROM VOH specifications : Microcontroller VOL specifications : Microcontroller IOL specifications
Example) When Vcc=5V, VOHM=5V, IOHM=0.4mA, VOLM=5V, IOLM=0.4mA,
From the equation , R R R VOHM IOHM 5 0.4x10
-3
From the equation, R R Vcc - VOLM IOLM 5 - 0.4 2.1x10 2.2 [k]
-3
12.5 [k]
R
Therefore, from the equations and , R 12.5 [k]
Fig.85 Circuit at DI, DO direct connection (Microcontroller DI/O "L" output, EEPROM "H" output)
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
19/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
Technical Note
7) Notes on power ON/OFF At power ON/OFF, set CS "L". When CS is "H", this IC gets in input accept status (active). If power is turned on in this status, noises and the likes may cause malfunction, mistake write or so. To prevent these, at power ON, set CS "L". (When CS is in "L" status, all inputs are cancelled.) And at power decline, owing to power line capacity and so forth, low power status may continue long. At this case too, owing to the same reason, malfunction, mistake write may occur, therefore, at power OFF too, set CS "L".
VCC VCC GND VCC CS GND Bad example Good example
Fig.86 Timing at power ON/OFF
Bad exampleCS pin is pulled up to Vcc.
In this case, CS becomes "H" (active status), and EEPROM may have malfunction, mistake write owing to noise and the likes. Even when CS input is High-Z, the status becomes like this case, which please note.
Good exampleIt is "L" at power ON/OFF.
Set 10ms or higher to recharge at power OFF. When power is turned on without observing this condition, IC internal circuit may not be reset, which please note.
POR citcuit This IC has a POR (Power On Reset) circuit as a mistake write countermeasure. After POR action, it gets in write disable status. The POR circuit is valid only when power is ON, and does not work when power is OFF. However, if CS is "H" at power ON/OFF, it may become write enable status owing to noises and the likes. For secure actions, observe the follwing conditions. 1. Set CS="L" 2. Turn on power so as to satisfy the recommended conditions of tR, tOFF, Vbot for POR circuit action.
VCC tR
Recommended conditions of tR, tOFF, Vbot
tR
tOFF Vbot
t O FF
V bot
10m s or below
10m s or higher 0.3V or below
0
100m s or below 10m s or higher 0.2V or below
LVCC circuit
Fig.87 Rise waveform diagram
LVCC (VCC-Lockout) circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ.=1.2V) or below, it prevent data rewrite.
8) Noise countermeasures VCC noise (bypass capacitor) When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a by pass capacitor (0.1F) between IC VCC and GND, At that moment, attach it as close to IC as possible.And, it is also recommended to attach a bypass capacitor between board VCC and GND. SK noise When the rise time (tR) of SK is long, and a certain degree or more of noise exists, malfunction may occur owing to clock bit displacement.To avoid this, a Schmitt trigger circuit is built in SK input. The hysteresis width of this circuit is set about 0.2V, if noises exist at SK input, set the noise amplitude 0.2Vp-p or below. And it is recommended to set the rise time (tR) of SK 100ns or below. In the case when the rise time is 100ns or higher, take sufficient noise countermeasures. Make the clock rise, fall time as small as possible.
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
20/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
Technical Note
Note ofn use (1) Described numeric values and data are design representative values, and the values are not guaranteed. (2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI. (3) Absolute Maximum Ratings If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI. (4) GND electric potential Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is not lower than that of GND terminal in consideration of transition status. (5) Heat design In consideration of allowable loss in actual use condition, carry out heat design with sufficient margin. (6) Terminal to terminal shortcircuit and wrong packaging When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be destructed. (7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
21/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series Serial EEPROM Series
Technical Note
High Reliability Series EEPROMs Microwire BUS
BR93H-WC Series
Description BR93H-WC Series is a serial EEPROM of serial 3-line interface method.
Features 1) Withstands electrostatic voltage 8kV, (twice more than other series)HBM method typ. 2) Wide action range -40+125-40+85, -40+105 in other series 3) Conforming to Microwire BUS 4) Highly reliable connection by Au pad and Au wire 5) Address auto increment function at read action 6) Write mistake prevention function Write prohibition at power on Write prohibition by command code Write mistake prevention circuit at low voltage 7) Program cycle auto delete and auto end function 8) Program condition display by READY / BUSY 9) Low current consumption At write action (at 5V) : 0.6mA (Typ.) At read action (at 5V) : 0.6mA (Typ.) At standby action (at 5V) : 0.1A (Typ.)(CMOS input) 10) Built-in noise filter CS, SK, DI terminals 11) Compact package SOP8/SOP-J8 12) High reliability by ROHM original Double-Cell structure 13) High reliability ultrafine CMOS process 14) Easily connectable with serial port BR93H series 15) Data retention for 40 years 16) Data rewrite up to 1,000,000 times 17) Data at shipment all address FFFFh
BR93H Series Capacity 2Kbit 4Kbit 8Kbit 16Kbit
Bit format 128x16 256x16 512x16 1Kx16
Type Package type BR93H56-WC BR93H66-WC BR93H76-WC BR93H86-WC
Power source voltage F 2.75.5V 2.75.5V 2.75.5V 2.75.5V
SOP8 RF
SOP-J8 FJ RFJ
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
22/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
Absolute Maximum Ratings (Ta=25) Parameter Impressed voltage Permissible dissipation Storage temperature range Action temperature range Terminal voltage
*When using at Ta=25 or higher, 4.5mW(*1,*2), to be reduced per 1.
Technical Note
Symbol VCC Pd Tstg Topr
Limits -0.3+6.5 560 (SOP8) -65+150 -40+125 -0.3VCC+0.3
*1 *2
Unit V mW V
560 (SOP-J8)
Memory cell characteristics (VCC=2.75.5V) Parameter Number of data rewrite times *1 Data hold years
*1
Min. 1,000,000 500,000 300,000 40 20
Limit Typ. -
Max. -
Limit Times Times Times Years Years
Limit Ta85 Ta105 Ta125 Ta25 Ta85
Not 100% TESTED
Recommended action conditions Parameter Power source voltage Input voltage
Symbol VCC VIN
Limits 2.75.5 0VCC
Unit V
Electrical characteristics (Unless otherwise specified, Ta=-40+125, VCC=2.75.5V) Limits Parameter Symbol Unit Conditions Min. Typ. Max. "L" input voltage VIL -0.3 0.3xVCC V "H" input voltage VIH 0.7xVCC VCC+0.3 V "L" output voltage 1 VOL1 0 0.4 V IOL=2.1mA, 4.0VVCC5.5V "L" output voltage 2 VOL2 0 0.2 V IOL=100A "H" output voltage 1 VOH1 2.4 VCC V IOH=-0.4mA, 4.0VVCC5.5V "H" output voltage 2 VOH2 VCC-0.2 VCC V IOH=-100A Input leak current ILI -10 10 A VIN=0VVCC Output leak current ILO -10 10 A VOUT=0VVCC, CS=0V ICC1 3.0 mA fSK=1.25MHz, tE/W=10ms (WRITE) Current consumption at ICC2 1.5 mA fSK=1.25MHz (READ) action ICC3 4.5 mA fSK=1.25MHz, tE/W=10ms (WRAL) Standby current ISB 0.1 10 A CS=0V, DO=OPEN
Radiation resistance design is not made.
Action timing characteristics (Unless otherwise specified, Ta=-40+125, VCC=2.75.5V) Parameter Symbol Min. Typ. SK frequency fSK SK "H" time tSKH 250 SK "L" time tSKL 250 CS "L" time tCS 200 CS setup time tCSS 200 DI setup time tDIS 100 CS hold time tCSH 0 DI hold time tDIH 100 Data "1" output delay time tPD1 Data "0" output delay time tPD0 Time from CS to output establishment tSV Time from CS to High-Z tDF Write cycle time tE/W 7
Max. 1.25 300 300 200 200 10
Unit MHz ns ns ns ns ns ns ns ns ns ns ns ms
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
23/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
Sync data input / output timing
Technical Note
CS
tCSS tSKH tSKL tCSH
SK
tDIS tDIH
DI
tPD0 tPD1
DO
(READ)
tDF
DO (WRITE)
STATUS VALID
Fig.1 Sync data input / output timing diagram
Data is taken by DI sync with the rise of SK. At read action, data is output from DO in sync with the rise of SK. The status signal at write (READY / BUSY) is output after tCS from the fall of CS after write command input, at the area DO where CS is "H", and valid until the next command start bit is input. And, white CS is "L", DO becomes High-Z. After completion of each mode execution, set CS "L" once for internal circuit reset, and execute the following action mode.
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
24/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
BR93H-WC Characteristic data
Technical Note
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
25/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
BR93H-WC Characteristic data
Technical Note
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
26/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
Block diagram
Technical Note
CS
Command decode Control
Power source voltage detection
SK
Clock generation
Write prohibition Address buffer
7bit 8bit 9bit 10bit
High voltage occurrence
DI
Command register
Address decoder
7bit 8bit 9bit 10bit
Data register DO Dummy bit
16bit
R/W amplifier
16bit
2,048 bit 4,096 bit 8,192 bit 16,384 bit EEPROM
Fig. 27 Block diagram Pin assignment and function
VCC NC TEST GND VCC TEST2 TEST1 GND
BR93H56RF-WC:SOP8 BR93H56RFJ-WC:SOP-J8
BR93H66RF-WC:SOP8 BR93H66RFJ-WC:SOP-J8 BR93H76RF-WC:SOP8 BR93H76RFJ-WC:SOP-J8 BR93H86RF-WC:SOP8 BR93H86RFJ-WC:SOP-J8
CS
SK
DI
DO
CS
SK
DI
DO
Fig.28 Pin assignment diagram
Pin name Vcc GND CS SK DI DO NC TEST1 TEST2 TEST
I/O Input Input Input Output -
Function Power source All input / output reference voltage, 0V Chip select input Serial clock input Start bit, ope code, address, and serial data input Serial data output, READY / BUSY internal condition display output Non connected terminal, Vcc, GND or OPEN TEST terminal, GND or OPEN TEST terminal, Vcc, GND or OPEN TEST terminal, GND or OPEN
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
27/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
Technical Note
Description of operations Communications of the Microwire Bus are carried out by SK (serial clock), DI (serial data input),DO (serial data output) ,and CS (chip select) for device selection. When to connect one EEPROM to a microcontroller, connect it as shown in Fig.29-(a) or Fig.29-(b). When to use the input and output common I/O port of the microcontroller, connect DI and DO via a resistor as shown in Fig.29-(b) (Refer to pages 31/35.), and connection by 3 lines is available. In the case of plural connections, refer to Fig. 29-(c).
Microcontroller CS SK DO DI Microcontroller CS SK DO Microcontroller BR93HXX CS SK DI
CS SK DI DO
BR93HXX CS SK DI DO
CS3 CS1 CS0 SK DO DI
DO
CS SK DI DO
Device 1
Device 2
Fig.29-(a) Connection by 4 lines Fig.29-(b) Connection by 3 lines
Fig.29-(c) Connection example of plural devices
Fig.29 Connection method with microcontroller Communications of the Microwire Bus are started by the first "1" input after the rise of CS. This input is called a start bit. After input of the start bit, input ope code, address and data. Address and data are input all in MSB first manners. "0" input after the rise of CS to the start bit input is all ignored. Therefore, when there is limitation in the bit width of PIO of the microcontroller, input "0" before the start bit input, to control the bit width. Command mode Command
Read (READ) Write enable (WEN) Write (WRITE) Write all (WRAL) Write disable (WDS)
*2 *2,3 *1
Start bit 1 1 1 1 1
Ope code 10 00 01 00 00
Address BR93H56/66-WC
A7,A6,A5,A4,A3,A2,A1,A0 1 1 ****** A7,A6,A5,A4,A3,A2,A1,A0 0 1 * * * * * B0 0 0 ******
BR93H76/86-WC
A9,A8,A7,A6,A5,A4,A3,A2,A1,A0 1 1 ******** A9,A8,A7,A6,A5,A4,A3,A2,A1,A0 0 1 * * * * * B2,B1,B0 0 0 ********
Data
D15~D0(READ DATA)
D15~D0(WRITE DATA) D15~D0(WRITE DATA)
Input the address and the data in MSB first manners. As for *, input either VIH or VIL. *Start bit Acceptance of all the commands of this IC starts at recognition of the start bit. The start bit means the first "1" input after the rise of CS.
A7 and B0 of BR93H56-WC becomes Don't Care. A9 and B2 of BR93H76-WC becomes Don't Care.
*1 As for read, by continuous SK clock input after setting the read command, data output of the set address starts, and address data in significant order are sequentially output continuously. (Auto increment function) *2 When the read and the write all commands are executed, data written in the selected memory cell is automatically deleted, and input data is written. *3 For the write all command, data written in memory cell of the areas designated by B2, B1, and B0, are automatically deleted, and input data is written in bulk.
Write all area B2 0 0 0 0 1 1 1 1 B1 B0 00 01 10 11 00 01 10 11 Write area 000h07Fh 080h0FFh 100h17Fh 180h1FFh 200h27Fh 280h2FFh 300h37Fh 380h3FFh
Designation of B2, B1, and B0 H56 H66 H76 H86 B2 B1 B1 B0 B0 B0
The write all command is written in bulk in 2Kbit unit. The write area can be selected up to 3bit. Confirm the settings and write areas of the above B2, B1, and B0.
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
28/40
2009.12 - Rev.E
CS SK DI DO
Device 3
BR93L-W Series, 93A-WM Series, BR93H-WC Series
Timing chart 1) Read cycle (READ)
CS
*1
Technical Note

SK
1
2
4
n
n+1
DI
1
1
0
Am

A1
A0
*2
BR93H56/66-WC : n=27, m=7 BR93H76/86-WC : n=29, m=9

DO High-Z
0
D15
D14
D1
D0
D15 D14
*2 The following address data output auto increment function
*1 Start bit When data "1" is input for the first time after the rise of CS, this is recognized as a start bit. And when "1" is input after plural "0" are input, it is recognized as a start bit, and the following operation is started. This is common to all the commands to described hereafter.
Fig. 30 Read cycle When the read command is recognized, input address data (16bit) is output to serial. And at that moment, at taking A0, in sync with the rise of SK, "0" (dummy bit) is output. And, the following data is output in sync with the rise of SK. This IC has address auto increment function valid only at read command. This is the function where after the above read execution, by continuously inputting SK clock, the above address data is read sequentially. And, during the auto increment, keep CS at "H". 2) Write cycle (WRITE)

CS

tCS
n
STATUS
SK DI DO
1
1
2
4
BR93H56/66-WC : n=27, m=7 BR93H76/86-WC : n=29, m=9
0
1
Am
A1
A0
D15
D14
D1
D0
tSV
BUSY
High-Z
READY
Fig. 31 Write cycle
tE/W
In this command, input 16bit data (D15~D0) are written to designated addresses (Am~A0). The actual write starts by the fall of CS of D0 taken SK clock(n-th clock from the start bit input), to the rise of the (n+1)-th clock. When STATUS is not detected, (CS="L" fixed) Max. 10ms in conformity with tE/W, and when STATUS is detected (CS="H"), all commands are not accepted for areas where "L" (BUSY) is output from D0, therefore, do not input any command. Write is not made even if CS is started after input of clock after (n+1)-th clocks.
Note) Take tSKH or more from the rise of the n-th clock to the fall of CS.
3) Write all cycyle (WRAL)
CS SK DI DO
1
1 2 5 m
tCS
STATUS
n
BR93H56/66-WC : n=27, m=9 BR93H76/86-WC : n=29, m=11
0
0
0
1
B2
B1
B0
D15
D1
D0 tSV
BUSY READY
High-Z
Fig. 32 Write all cycle
tE/W
In this command, input 16bit data is written simultaneously to designated block for 128 words. Data is writen in bulk at a write time of only Max. 10ms in conformity with tE/W. When writing data to all addresses, designate each block by B2, B1, and B0, and execute write. Write time is Max.10ms. The actual write starts by the fall of CS from the rise of D0 taken at SK clock (n-th clock from the start bit input), to the rise of the (n+1)-th clock. When CS is ended after clock input after the rise of the (n+1)-th clock, command is cancelled, and write is not completed.
Note)Take tSKH or more from the rise of the n-th clock to the fall of CS.
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
29/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
4) Write enable (WEN) / disable (WDS) cycle
Technical Note
CS
SK
1
2
3
4
5
6
7
8
n
ENABLE=1 1 DISABLE=0 0 DI 1 0 0
BR93H56/66-WC : n=11 BR93H76/86-WC : n=13

DO High-Z
Fig. 33 Write enable (WEN) / disable (WDS) cycle At power on, this IC is in write disable status by the internal RESET circuit. Before executing the write command, it is necessary to execute the write enable command. And, once this command is executed, it is valid unitl the write disable command is executed or the power is turned off. However, the read command is valid irrespective of write enable / disable command. Input to SK after 6 clocks of this command is available by either "H" or "L", but be sure to input it. When the write enable command is executed after power on, write enable status gets in. When the write disable command is executed then, the IC gets in write disable status as same as at power on, and then the write command is cancelled thereafter in software manner. However, the read command is executable. In write enable status, even when the write command is input by mistake, write is started. To prevent such a mistake, it is recommended to execute the write disable command after completion of write. Application 1) Method to cancel each command READ
Start bit
1bit
Ope code
2bit
Address
8bit
*1
Data
16bit
*1 Address is 8 bits in BR93H56-WC, and BR93H66-WC. Address is 10 bits in BR93H76-WC, and BR93H86-WC.
Cancel is available in all areas in read mode. Method to cancelcancel by CS="L"
Fig.34 READ cancel available timing WRITE, WRAL
Rise of 27clock
*2
SK DI
26 D1 a
27 D0 b
28 c
29
Enlarged figure
Start bit
1bit
Ope code
2bit
Address
8bit
*1
Data
16bit
tE/W
C
*1 Address is 8 bits in BR93H56/66-WC Address is 10 bits in BR93H76/86-WC *2 27 clocks in BR93H56/66-WC 29 clocks in BR93H76/86-WC *3 28 clocks in BR93H56/66-WC 30 clocks in BR93H76/86-WC Note 1) If Vcc is made OFF in this area, designated address data is not guaranteed, therefore write once again. Note 2) If CS is started at the same timing as that of the SK rise, write execution/cancel becomes unstable, therefore, it is recommended to fail in SK="L" area. As for SK rise, recommend timing of tCSS/tCSH or higher.
a
aFrom start bit to 27 clock rise Cancel by CS="L"
b
b27 clock rise and after *2 Cancellation is not available by any means. If Vcc is made OFF in this area, designated address data is not guaranteed, therefore write once again. c28 clock rise and after *3 Cancel by CS="L" However, when write is started in b area (CS is ended), cancellation is not available by any means. And when SK clock is input continuously, cancellation is not available.
Fig.35 WRITE, WRAL cancel available timing
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
30/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
2) Equivalent circuit Output circuit
DO
Technical Note
OEint.
Fig.36 Output circuit (DO) Input circuit
RESET int. CS LPF CSint. EN
TEST1 (TEST)
TESTint.
Fig.37 Input circuit (CS)
EN SK DI SK(DI)int.
Fig.38
LPF
Input circuit (TEST1, TEST)
TEST2
Fig.39 3)
Input circuit (SK, DI)
Fig.40 Input circuit (TEST2)
I/O peripheral circuit 3-1) Pull down CS. By making CS="L" at power ON/OFF, mistake in operation and mistake write are prevented. Refer to the item 6) Notes at power ON/OFF in page 34/35. Pull down resistance Rpd of CS pin To prevent mistake in operation and mistake write at power ON/OFF, CS pull down resistance is necessary. Select an appropriate value to this resistance value from microcontroller VOH, IOH, and VIL characteristics of this IC.
Rpd
Microcontroller VOHM EEPROM VIHE
VOHM IOHM VIHE

VOHM
Example) When VCC =5V, VIHE=2V, VOHM=2.4V, IOHM=2mA, from the equation , Rpd Rpd 2.4 2x10
-3
"H" output
IOHM
Rpd
"L" input
1.2 [k]
With the value of Rpd to satisfy the above equation, VOHM becomes 2.4V or higher, and VIHE (=2.0V), the equation is also satisfied.
Fig.41 CS pull down resistance
VIHE VOHM IOHM
: EEPROM VIH specifications : Microcontroller VOH specifications :Microcontroller IOH specifications
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
31/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
Technical Note
3-2) DO is available in both pull up and pull down. Do output become "High-Z" in other READY / BUSY output timing than after data output at read command and write command. When malfunction occurs at "High-Z" input of the microcontroller port connected to DO, it is necessary to pull down and pull up DO. When there is no influence upon the microcontroller actions, DO may be OPEN. If DO is OPEN, and at timing to output status READY, at timing of CS="H", SK="H", DI="H", EEPROM recognizes thisas a start bit, resets READY output, and DO="High-Z", therefore, READY signal cannot be detected. To avoid such output, pull up DO pin for improvement.
CS CS "H"
SK Enlarged DI D0
SK
DI
High-Z DO
BUSY
READY
DO BUSY
High-Z
CS=SK=DI="H" When DO=OPEN CS=SK=DI="H" When DO=pull up
Improvement by DO pull up DO
BUSY READY
Fig.42 READY output timing at DO=OPEN
Pull up resistance Rpu and pull down resistance Rpd of DO pin As for pull up and pull down resistance value, select an appropriate value to this resistance value from microcontroller VIH, VIL, and VOH, IOH, VOL, IOL characteristics of this IC.
Rpu
Microcontroller VILM Rpu IOLE VOLE EEPROM
VccVOLE IOLE VILM

VOLE
Example) When VCC =5V, VOLE=0.4V, IOLE=2.1mA, VILM=0.8V, from the equation , Rpu 50.4 2.1x10 2.2 [k]
-3
"L" input "L" output
Rpu
VOLE IOLE VILM
With the value of Rpu to satisfy the above equation, VOLE becomes 0.4V or below, and with VILM(=0.8V), the equation is also satisfied. VOLE : EEPROM VOL specifications IOLE : EEPROM IOL specifications VILM : Microcontroller VIL specifications VOHE IOHE VIHM
Fig.43 DO pull up resistance
Rpd
Microcontroller VIHM IOHE EEPROM

VOHE
VOHE Rpd "H" output
Example) When VCC =5V, VOHE=Vcc0.2V, IOHE=0.1mA, VIHM=Vccx0.7V from the equation Rpd Rpd 50.2 0.1x10 48 [k]
-3
"H" input
With the value of Rpd to satisfy the above equation, VOHE becomes 2.4V or below, and with VIHM (=3.5V), the equation is also satisfied.
Fig.44 DO pull down resistance
VOHE : EEPROM VOH specifications IOHE : EEPROM IOH specifications VIHM : Microcontroller VIH specifications
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
32/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
READY / BUSY status display (DO terminal) (common to BR93H56-WC, BR93H66-WC, BR93H76-WC, BR93H86-WC)
This display outputs the internal status signal. When CS is started after tCS (Min.200ns) from CS fall after write command input, "H" or "L" output.
Technical Note
DO status
R/B display"L" (BUSY) = write under execution After the timer circuit in the IC works and creates the period of tE/W, this time circuit completes automatically. And write to the memory cell is made in the period of tE/W, and during this period, other command is not accepted. R/B display = "H" (READY) = command wait status Even after tE/W (max.10ms) from write of the memory cell, the following command is accepted. Therefore, CS="H" in the period of tE/W, and when input is in SK, DI, malfunction may occur, therefore, DI="L" in the area CS="H". (Especially, in the case of shared input port, attention is required.)
DO status
*Do not input any command while status signal is output. Command input in BUSY area is cancelled, but command input in READY area is accepted. Therefore, status READY output is cancelled, and malfunction and mistake write may be made.
CS
STATUS
SK
CLOCK WRITE INSTRUCTION High-Z
DI
DO
tSV
READY BUSY
Fig.45 R/B status output timing chart 4) When to directly connect DI and DO This IC has independent input terminal DI and output terminal DO, and separate signals are handled on timing chart, meanwhile, by inserting a resistance R between these DI and DO terminals, it is possible to carry out control by 1 control line.
Microcontroller DI/O PORT DI R DO EEPROM
Fig.46 DI, DO control line common connection Data collision of microcontroller DI/O output and DO output and feedback of DO output to DI input. Drive from the microcontroller DI/O output to DI input on I/O timing, and signal output from DO output occur at the same time in the following points. 4-1) 1 clock cycle to take in A0 address data at read command Dummy bit "0" is output to DO terminal. When address data A0 = "1" input, through current route occurs.
EEPROM CS input "H"
EEPROM SK input A1 A0 Collision of DI input and DO output EEPROM DO output High-Z A1 A0 0 D15 D14 D13
EEPROM DI input
Microcontroller DI/O port
High-Z Microcontroller input
Microcontroller output
Fig.47 Collision timing at read data output at DI, DO direct connection
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
33/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
Technical Note
4-2) Timing of CS = "H" after write command. DO terminal in READY / BUSY function output. When the next start bit input is recognized, "HIGH-Z" gets in. Especially, at command input after write, when CS input is started with microcontroller DI/O output "L", READY output "H" is output from DO terminal, and through current route occurs. Feedback input at timing of these 4-1) and 4-2) does not cause disorder in basic operations, if resistance R is inserted.
EEPROM CS input
Write command

EEPROM SK input
Write command

EEPROM DI input
Write command READY
EEPROM DO output
Write command
BUSY
READY
High-Z
Collision of DI input and DO output
Microcontroller DI/O port
Write command Microcontroller output
BUSY
READY
Microcontroller input
Microcontroller output
Fig.48 Collision timing at DI, DO direct connection Selection of resistance value R The resistance R becomes through current limit resistance at data collision. When through current flows, noises of power source line and instantaneous stop of power source may occur. When allowable through current is defined as I, the following relation should be satisfied. Determine allowable current amount in consideration of impedance and so forth of power source line in set. And insert resistance R, and set the value R to satisfy EEPROM input level VIH/VIL, even under influence of voltage decline owing to leak current and so forth. Insertion of R will not cause any influence upon basic operations. 4-3) Address data A0 = "1" input, dummy bit "0" output timing (When microcontroller DI/O output is "H", EEPROM DO outputs "L", and "H" is input to DI) Make the through current to EEPROM 10mA or below. See to it that the input level VIH of EEPROM should satisfy the following.
Conditions
Microcontroller EEPROM
VOHM VIHE VOHM IOHMxR + VOLE At this moment, if VOLE=0V, VOHM IOHMxR
DI/O PORT "H" output VOHM IOHM R
DI
DO VOLE "L" output
VIHE VOLE VOHM IOHM
R
VOHM IOHM
: EEPROM VIH specifications : EEPROM VOL specifications : Microcontroller VOH specifications : Microcontroller IOH specifications
Fig.49
Circuit at DI, DO direct connection (Microcontroller DI/O "H" output, EEPROM "L" output)
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
34/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
4-4) DO status READY output timing (When the microcontroller DI/O is "L", EEPROM DO outputs "H", and "L" is input to DI) Set the EEPROM input level VIL so as to satisfy the following.
Conditions
Microcontroller "L" output DI/O PORT VOLM IOHM R DO VOHE "H" output DI EEPROM
Technical Note
VOLM VILE VOLM VOHE - IOLMxR As this moment, if VOHE=Vcc, VOLM Vcc - IOLMxR VILE VOHE VOLM IOLM R Vcc - VOLM IOLM
: EEPROM VIL specifications : EEPROM VOH specifications : Microcontroller VOL specifications : Microcontroller IOL specifications
Example) When Vcc=5V, VOHM=5V, IOHM=0.4mA, VOLM=5V, IOLM=0.4mA,
From the equation , R R R VOHM IOHM 5 0.4x10
-3
From the equation , R R Vcc - VOLM IOLM 5 - 0.4 2.1x10 2.2 [k]
-3
12.5 [k]
R
Therefore, from the equations and , R 12.5 [k]
Fig.50
Circuit at DI, DO direct connection (Microcontroller DI/O "L" output, EEPROM "H" output)
5) Notes at test pin wrong input There is no influence of external input upon TEST2 pin. For TEST1 (TEST)pin, input must be GND or OPEN. If H level is input, the following may occur, 1. At WEN, WDS, READ command input There is no influence by TEST1 (TEST) pin.
2. WRITE, WRAL command input
* BR93H56-WC, BR93H66-WC, address 8 bits BR93H76-WC, BR93H86-WC, address 10 bits
Start bit
Ope code
Address*
Data
tE/W
1bits
2bits
a
8bits
16bits Write start CS rise timing
Fig.51 TEST1(TEST) pin wrong input timing aThere is no influence by TEST1 (TEST) pin.
bIf H during write execution, it may not be written correctly. And H area remains BUSY and READY does not go back. Avoid noise input, and at use, be sure to connect it to GND terminal or set it OPEN.
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
35/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
Technical Note
6) Notes on power ON/OFF At power ON/OFF, set CS "L". When CS is "H", this IC gets in input accept status (active). At power ON, set CS "L" to prevent malfunction from noise. (When CS is in "L" status, all inputs are cancelled.) At power decline low power status may prevail. Therefore, at power OFF, set CS "L" to prevent malfunction from noise.
VCC VCC GND VCC CS GND Bad example Good example
Fig.52 Timing at power ON/OFF
Bad exampleCS pin is pulled up to Vcc. In this case, CS becomes "H" (active status), EEPROM may malfunction or have write error due to noises. This is true even when CS input is High-Z. Good exampleIt is "L" at power ON/OFF. Set 10ms or higher to recharge at power OFF. When power is turned on without observing this condition, IC internal circuit may not be reset.
POR citcuit This IC has a POR (Power On Reset) circuit as a mistake write countermeasure. After POR action, it gets in write disable status. The POR circuit is valid only when power is ON, and does not work when power is OFF. However, if CS is "H" at power ON/OFF, it may become write enable status owing to noises and the likes. For secure actions, observe the follwing conditions. 1. Set CS="L" 2. Turn on power so as to satisfy the recommended conditions of tR, tOFF, Vbot for POR circuit action.
VCC tR
Recommended conditions of tR, tOFF, Vbot
tR 10m s or below
tOFF Vbot
t O FF
V bot
10m s or higher 0.3V or below
100m s or below 10m s or higher 0.2V or below
0
Fig.53 Rise waveform diagram LVCC circuit LVCC (VCC-Lockout) circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ.=1.9V) or below, it prevent data rewrite. 7) Noise countermeasures VCC noise (bypass capacitor) When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a by pass capacitor (0.1F) between IC VCC and GND, At that moment, attach it as close to IC as possible.And, it is also recommended to attach a bypass capacitor between board VCC and GND. SK noise When the rise time (tR) of SK is long, and a certain degree or more of noise exists, malfunction may occur owing to clock bit displacement. To avoid this, a Schmitt trigger circuit is built in SK input. The hysteresis width of this circuit is set about 0.2V, if noises exist at SK input, set the noise amplitude 0.2Vp-p or below. And it is recommended to set the rise time (tR) of SK 100ns or below. In the case when the rise time is 100ns or higher, take sufficient noise countermeasures. Make the clock rise, fall time as small as possible.
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
36/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
Technical Note
Cautions on use (1) Described numeric values and data are design representative values, and the values are not guaranteed. (2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI. (3) Absolute Maximum Ratings If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI. (4) GND electric potential Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is not lower than that of GND terminal in consideration of transition status. (5) Heat design In consideration of allowable loss in actual use condition, carry out heat design with sufficient margin. (6) Terminal to terminal shortcircuit and wrong packaging When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be destructed. (7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
37/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
Technical Note
B
R
9
3
L
4
Capacity
46=1K 56=2K 66=4K 76=8K 86=16K
6
F
J
-
W
Double cell L:W A:WM H:WC
E
2
ROHM Type name
BUSType Operating 93Microwire temperature L:-40~+85 A:-40~+105 H:-40~+125
Package type F,RF :SOP8 FJ,RFJ :SOP-J8 FV,RFV : SSOP-B8 FVT,RFVT : TSSOP-B8 RFVJ : TSSOP-B8J RFVM : MSOP8
Package specifications E2reel shape emboss taping TRreel shape emboss taping
SOP8

5.00.2 (MAX 5.35 include BURR)
8 7 6 5
+6 4 -4
Tape Quantity
0.90.15 0.3MIN
Embossed carrier tape 2500pcs E2
The direction is the 1pin of product is at the upper left when you hold
6.20.3
4.40.2
Direction of feed
( reel on the left hand and you pull out the tape on the right hand
)
12
3
4
0.595
1.50.1
+0.1 0.17 -0.05 S
0.11
1.27 0.420.1
1pin
(Unit : mm)
Direction of feed
Reel
Order quantity needs to be multiple of the minimum quantity.
SOP-J8
4.90.2 (MAX 5.25 include BURR) +6 4 -4
8 7 6 5

Tape Quantity
0.45MIN
Embossed carrier tape 2500pcs E2
The direction is the 1pin of product is at the upper left when you hold
6.00.3
3.90.2
Direction of feed
( reel on the left hand and you pull out the tape on the right hand
)
1
2
3
4
0.545 S
0.20.1
1.3750.1
0.175
1.27 0.420.1 0.1 S
1pin (Unit : mm) Reel
Direction of feed
Order quantity needs to be multiple of the minimum quantity.
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
38/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
Technical Note
SSOP-B8

3.0 0.2 (MAX 3.35 include BURR)
876 5
Tape Quantity
0.3MIN
Embossed carrier tape 2500pcs E2
The direction is the 1pin of product is at the upper left when you hold
6.40.3
4.40.2
Direction of feed
( reel on the left hand and you pull out the tape on the right hand
)
1234
1.150.1
0.15 0.1 S 0.1 +0.06 0.22 -0.04 0.08
M
0.1
(0.52)
0.65
1pin
(Unit : mm)
Direction of feed
Reel
Order quantity needs to be multiple of the minimum quantity.
TSSOP-B8
3.0 0.1 (MAX 3.35 include BURR)
8 7 6 5

44
Tape Quantity
Embossed carrier tape 3000pcs E2
The direction is the 1pin of product is at the upper left when you hold
6.40.2 4.40.1
Direction of feed
0.50.15 1.00.2
( reel on the left hand and you pull out the tape on the right hand
)
1
2
3
4
1.00.05
1.2MAX
0.525
1PIN MARK S
+0.05 0.145 -0.03
0.10.05
0.08 S +0.05 0.245 -0.04 0.65
0.08
M
1pin
(Unit : mm)
Direction of feed
Reel
Order quantity needs to be multiple of the minimum quantity.
TSSOP-B8J
3.0 0.1 (MAX 3.35 include BURR)
8 7 6 5

44
Tape Quantity
Embossed carrier tape 2500pcs E2
The direction is the 1pin of product is at the upper left when you hold
4.90.2
3.00.1
0.450.15
Direction of feed
0.950.2
( reel on the left hand and you pull out the tape on the right hand
)
1
2
3
1PIN MARK S
4
0.850.05
1.1MAX
0.525
+0.05 0.145 - 0.03
0.10.05
0.08 S +0.05 0.32 -0.04 0.65 0.08
M
1pin
(Unit : mm)
Direction of feed
Reel
Order quantity needs to be multiple of the minimum quantity.
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
39/40
2009.12 - Rev.E
BR93L-W Series, 93A-WM Series, BR93H-WC Series
Technical Note
MSOP8

2.90.1 (MAX 3.25 include BURR)
8765
Tape
0.290.15 0.60.2
+6 4 -4
Embossed carrier tape 3000pcs TR
The direction is the 1pin of product is at the upper right when you hold
Quantity Direction of feed
4.00.2
2.80.1
( reel on the left hand and you pull out the tape on the right hand
1pin
)
1 234
1PIN MARK 0.475 S +0.05 0.22 -0.04 0.08 S 0.65
+0.05 0.145 -0.03
0.9MAX 0.750.05
0.080.05
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
40/40
2009.12 - Rev.E
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us.
ROHM Customer Support System
http://www.rohm.com/contact/
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
R0039A

▲Up To Search▲

Price & Availability of BR93A86-WM

	To Download BR93A86-WM Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .